The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to a process or method for controlled etching through an IC structure which has two or more materials arranged together, and where the height of one of the materials may need to be modulated relative to the other materials.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit such as a memory cell, multiple deposition and/or etching steps may be employed. By way of example, one method of etching is plasma etching. In plasma etching, a plasma is formed from the ionization and dissociation of process gases. The positively charged ions are accelerated towards the substrate where they, in combination with neutral species, drive the etching reactions. In this manner, etched features such as vias, contacts, or trenches may be formed in the layers of the substrate.
Recently, shallow trench isolation (STI) has grown in popularity as a preferred method for forming a trench that can, among other applications, electrically isolate individual transistors in an integrated circuit. Electrical isolation is needed to prevent current leakage between two adjacent devices (e.g., transistors). Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask over the targeted trench layer, patterning a soft mask over the hard mask, etching the hard mask through the soft mask to form a patterned hard mask, and thereafter etching the targeted trench layer to form the shallow trench isolation feature. Subsequently, the soft mask is removed (e.g., stripped) and the shallow trench isolation feature is back-filled with a dielectric material.
FIGS. 1A-1C are cross sectional views of the conventional process steps that maybe used to form shallow trench isolation features. Referring initially to FIG. 1A, there is shown a typical layer stack 10 that is part of a substrate or semiconductor wafer (not drawn to scale for ease of illustration). A silicon layer 12 is located at the bottom of layer stack 10. A pad oxide layer 14 is formed above silicon layer 12 and a nitride layer 16 is formed above pad oxide layer 14. In most situations, the pad oxide layer is used as the interlayer that is disposed between the nitride layer and the silicon layer. Furthermore, in order to create a patterned hard mask with pad oxide layer 14 and nitride layer 16, a photoresist layer 18 is deposited and patterned using a conventional photolithography step over nitride layer 16. After patterning, soft mask openings 20 (narrow) and 22 (wide) are created in photoresist layer 18 to facilitate subsequent etching. The above-described layers and features, as well as the processes involved in their creation, are well known to those skilled in the art.
Following the formation of layer stack 10, nitride layer 16 and pad oxide 14 are subsequently etched to create a hard mask, which includes a narrow hard mask opening 24 and a wide hard mask opening 26, as seen in FIG. 1B. The hard mask openings are used to pattern the trench during etching of the silicon layer. For the most part, etching stops after reaching silicon layer 12, however, a small portion 28 on the surface of silicon layer 12 is typically etched away during the etching of pad oxide layer 14. Moreover, a gas chemistry that includes CF4 is generally used to facilitate etching through the nitride and pad oxide layers. Typically, the CF4 chemistry etches the side walls of nitride layer 16, pad oxide layer 14 and small portion 28 of silicon layer 12 anisotropically (i.e., substantially straight down).
Once hard mask openings are created through nitride layer 16 and pad oxide layer 14, silicon layer 12 is etched therethrough to form shallow trench isolation features, for example, a narrow feature 30 and a wide feature 32, as shown in FIG. 1C. Typically, a gas chemistry that includes Cl.sub.2 and/or HBr is used to facilitate etching through the silicon layer. Subsequent to the steps shown in FIGS. 1B & 1C, the mask layers are removed, leaving a trench disposed in the silicon layer. Typically, thereafter, the trenches are filled with a dielectric material such as an oxide (e.g., TEOS) to complete the formation of the shallow trench isolation. In general, the depth of the etch is controlled as a function of the etchant chemistry, and the amount of time involved in applying the etchant chemistry.
Among many process applications for STI techniques, the formation of Dynamic random access memory (DRAM) is one common example. DRAM is a kind of random access memory (RAM) for personal computers and workstations. Memory is the network of electrically-charged points in which a computer stores quickly accessible data in the form of 0s and 1s. Random access means that the PC processor can access any part of the memory or data storage space directly rather than having to proceed sequentially from some starting place. DRAM is dynamic in that, unlike static RAM (SRAM), the device needs to have its storage cells refreshed or given a new electronic charge every few milliseconds.
In general, two types of structures are used in DRAM manufacturing: (1) stacked capacitors, and (2) deep-trench capacitors. In a deep-trench capacitor structure, a poly-silicon material is embedded within (or adjacent to) a single-crystal silicon material. A cylinder of oxide material is formed adjacent to the poly-silicon material to thereby form an outer periphery (or collar) that extends to a certain depth. Note that in a DRAM cell, the collar is used in the formation of a capacitor that stores a charge. This charge is the physical occurrence of the data being stored in memory. The collar is an integral part of creating this capacitor cell. The collar serves as an isolation structure that allows individual contact with the memory cells. The collar is formed after most of the cell has been manufactured, and is germane to manufacture of this type of deep trench memory cell.
The etching process is thereby complicated by the need to etch both a single-crystal silicon substance and a poly-silicon substance within the same wafer. Moreover, as the etch proceeds downward, the oxide collar is encountered and must similarly be etched. In the end, the trenches are etched to a certain target depth. However, a certain amount of the oxide collar should remain above the etched surface for operational and contact purposes. Hence, in order to etch such a device, the etching process must be able to simultaneously etch through two or more different substances, i.e. single crystalline silicon, poly-crystalline silicon, and/or silicon dioxide (i.e. "oxide").
In a majority of prior art applications, the etching process has attempted to etch down through the various layers with near even selectivity. In other words, the etching process uses a chemistry that etches away all encountered substances at a near equal rate. With the etch rates for the example materials (i.e. crystal silicon, poly silicon, and/or oxide) as close to 1-to-1 as possible, a trench can be etched down to a desired level in only one process step. This is advantageous in that a single process step is much simpler (i.e. less costly and time consuming) to implement and execute.
In using such one step approaches, however, prior art applications have trouble independently controlling or modulating the height of the collar (or other such device that might extend above the level of the etched plane). By etching all materials simultaneously, the entire plane of the etched surface will generally be at one depth, with no differentiation between the etched height of the different IC structure materials.
Still another prior art technique uses a hard mask over various surface areas in order to etch different parts of the surface down to different levels. While generally effective to isolate surface areas, this technique is relatively more expensive and difficult to implement. Extra process steps are involved in placing and using the mask over the surface, and such steps add extra expense and difficulty in implementation.
A further prior art technique that might relate to the solution proposed by the present invention involves the formation of deep trenches in IC materials. In order to form relatively deep trenches (i.e. 100 angstroms, for micro-machining, and the like), the process switches back and forth between different chemistries in forming the trench. A first chemistry would be used for etching. A second passivating layer would be added to coat the side walls of the structure. Etching is again performed and vice versa until the proper trench depth is achieved. The general purpose of this technique is to preserve the sidewall structures of the device. While the technique switches back and forth between different chemistries, it does not perform etching with each step, and with each different chemistry. As a result, this technique does not address etching different materials that might be formed adjacent, or embedded within one another, as per the inventive technique below.
In view of the foregoing, there are desired improved techniques for etching an IC structure that has two or more (adjacent or embedded) materials to be etched down to a target level. In particular, a technique is desired that will allow modulation or control over the height of an embedded material such as an oxide collar. The process should allow use of either a resist mask, or a hard mask, while maintaining certain profile requirements. Also desired are etch techniques that may be implemented "in situ" (all processing performed in one plasma processing chamber), or "ex situ" (certain isolated processing steps performed in different plasma processing chambers).